Circuit Board Design Articles and Commentary
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Posted by Rick Austin on Fri, Apr 11, 2008 @ 12:42 PM
Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules
DDR2 pushed memory clock frequencies to 400 MHz and data rates to 800 Mbps. DDR3 further pushes clock frequencies to 800 MHz, while DDR4 is up to 1.6 GHz. New packaging technologies such as die stacking and package-on-package (PoP) are being developed to accommodate the advances.
Dr. Frank Y. Yuan and Richard Crisp - Tessera Inc.
Posted: 1-Apr 2008
Posted by Rick Austin on Tue, Apr 08, 2008 @ 07:04 PM
Posted by Rick Austin on Wed, Apr 02, 2008 @ 07:08 PM
Laser Direct Imaging Made EasyWith over 400 installations worldwide, LDI is gaining global market acceptance. Guy Alon and dr. Ralph Birnbaum, Orbotech Posted: 1Apr08
Posted by Rick Austin on Fri, Mar 28, 2008 @ 08:06 PM
Implementation of Buried Capacitance in High-Speed Designs
Embedded capacitance frees up the board surface for routing traces, can reduce the overall board size and can speed time to market.
Jun Fan, Norm Smith, Jim Knighten, John Andresakis, Yoshi Fukawa and Mark Harvey.
Posted: 1 March 2008
Posted by Rick Austin on Tue, Mar 25, 2008 @ 07:24 AM
Challenges in Implementing DDR3 Memory Interface on PCB Systems Undoubtedly faster, larger and lower power per bit, but just how do you go about interfacing a DDR3 SDRAM DIMM to an FPGA? The DDR3 standard addresses the faster, more bandwidth and lower power per bit need, but it introduces new design challenges in addition to challenges introduced by DDR2 ODT, slew rate derating, etc. The DDR2 fly-by topology requirement means customers designing DDR3 memories must now account for write leveling and read de-skew on the PCB. This paper, presented at DesignCon 2008, will cover modeling, simulation, and physical layout approaches required to meet JEDEC-defined termination and tight timing requirments for designing DDR3 memory interfaces on PCB systems. Phil Murray, Altera Corporation Feras Al-Hawari, Cadence Design Systems Posted: Feb 2008
Posted by Rick Austin on Thu, Mar 20, 2008 @ 03:20 PM
Chip Packaging 2.0 Provides Benefits to Board Designers"In Chip Packaging 2.0, we ask the question 'What if board designers were empowered to remap legacy package pinouts (without changing the performance of the silicon) to design optimum PCBs?'" by Ken Gilleo, ET-Trends Martin Hart, Mirror Semiconductor Posted: March 1, 2008
Posted by Rick Austin on Mon, Mar 17, 2008 @ 07:48 AM
Posted by Rick Austin on Fri, Mar 14, 2008 @ 08:28 AM
Flexible Thinking: Back to Basics Part 20
"In Part 19 of this series, the discussion centered on surface mount land terminations for flexible circuits and reviewed the synergistic relationship between flexible circuits and surface mount technology. In this part of the Back to Basics series, I turn our attention to the important matter of designing lands for flex circuits having plated through-holes." by Joseph Fjelstad, Silicon Pipe Inc Posted: 1 March 2008
Posted by Rick Austin on Mon, Mar 10, 2008 @ 08:13 AM
Posted by Rick Austin on Wed, Mar 05, 2008 @ 07:11 AM
TDR: taking the pulse of signal integrity
Time-domain reflectometry will help you design and troubleshoot cables, connectors, fast PCB traces, and high-speed packages. With TDR instruments, you can ensure the signal integrity of fast digital signals as they travel across your system. Both analog and digital engineers need to understand and use these techniques.
By Paul Rako, EDN Technical Editor
Posted: 3 September 2007
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